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ELECTRICAL DATA S3C2410A
24-24
SCLK
nSRAS
tSAD
Trp
nSCAS
DATA
ADDR/BA
nBEx
tSRD
SCKE
A10/AP
nGCSx
tSCSD
nWE
tSAD
tSCD
tSWD
tSAD
tSCSD
tSRD
'1'
'1'
'HZ'
Trc
tCKED
'HZ'
'1'
'1'
'1'
'1'
'1'
tCKED
NOTE:
Before executing auto/self refresh command, all banks must be in idle state.
Figure 24-26. SDRAM Self Refresh Timing (Trp = 2, Trc = 4)