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ARM920T PROCESSOR PROGRAMMER'S MODEL
2-17
The operations which can be carried out upon a single cache line identify the line using the data passed in the MCR
instruction. The data is interpreted using one of the following formats:
31
0
4 3 0
Modified virtual address
5
0000
2 1
SBZ
Figure 2-2. Register 7 MVA Format
31 19 1516 111221 20
0 0
8 7 4 3 0
0 0 0 00Index 0
26 25 24 23 10 9 5
0 0 0 0
2 1
Segment00000000
13141718
0 0 0
22
SBZSBZ
Figure 2-3. Register 7 Index Format
The use of register 7 is discussed in Chapter 4 Caches, Write Buffer and Physical Address TAG (PATAG) RAM.