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S3C2410A ELECTRICAL DATA
24-15
HCLK
nGCSx
nOE
Tacc = 6cycle
nWait
DATA
ADDR
Tacs
Tcos
delayed
NOTE:
The status of nWait is checked at (Tacc-1) cycle.
sampling nWait
3nS
Figure 24-15. External nWAIT READ Timing
(Tacs = 1, Tcos = 1, Tacc = 4, Tcoh = 0, Tcah = 1, PMC = 0, ST = 0)
HCLK
nGCSx
nWE
DATA
ADDR
tRDD
tRDD
Tacc >= 4 cycles
nWait
tWS
tWH
Figure 24-16. External nWAIT WRITE Timing
(Tacs = 0, Tcos = 0, Tacc = 4, Tcoh = 0, Tcah = 0, PMC = 0, ST = 0)