Filter
Top Products
ARM920T PROCESSOR CACHES, WRITE BUFFER
4-5
DATA CACHE AND WRITE BUFFER
The ARM920T includes a 16KB data cache and a write buffer to reduce the effect of main memory bandwidth and
latency on data access performance. The DCache has 512 lines of 32 bytes (8-words), arranged as a 64-way set-
associative cache and uses virtual addresses from the ARM9TDMI CPU core. The write buffer can hold up to 16
words of data and 4 separate addresses. The operation of the data cache and write buffer are intimately connected.
The DCache supports write-through (WT) and writeback (WB) memory regions, controlled by the C and B bits in
each section and page descriptor within the MMU translation tables. For clarity, these bits are referred to as Ctt and
Btt in the following text. For details see Data cache and write buffer operation on page 4-6.
Each DCache line has two dirty bits, one for the first 4-words of the line, the other for the last 4-words, and a single
virtual TAG address and valid bit for the entire 8-word line. The physical address from which each line was loaded is
stored in the PA TAG RAM and is used when writing modified lines back to memory.
A linefill always loads a complete 8-word line.
When a store hits in the DCache, if the memory region is WB, the associated dirty bit is set marking the appropriate
half-line as being modified. If the cache line is replaced due to a linefill, or if the line is the target of a DCache clean
operation, the dirty bits are used to decide whether the whole, half, or none of the line is written back to memory. The
line is written back to the same physical address from which it was loaded, regardless of any changes to the MMU
translation tables.
The DCache implements allocate-on-read-miss. Random or round-robin replacement can be selected under software
control via the RR bit (CP15 register 1, bit 14). Random replacement is selected at reset.
Data can also be locked in the DCache such that it cannot be overwritten by a linefill. This operates with a granularity
of 1/64th of the cache, which is 64 words (256 bytes).
All data accesses are subject to MMU permission and translation checks. Data accesses which are aborted by the
MMU will not cause linefills or data accesses to appear on the ASB.
For clarity, the C bit (bit 2 in CP15 register 1) is referred to as the Ccr bit throughout the following text.