Filter
Top Products
ARM920T PROCESSOR CACHES, WRITE BUFFER
4-11
Situations which necessitate cache cleaning and invalidating include:
• writing instructions to a cacheable area of memory using STR or STM instructions, for example:
— self-modifying code
— JIT compilation
— copying code from another location
— downloading code via the EmbeddedICE JTAG debug features
— updating an exception vector entry.
• another bus master, such as a DMA controller, modifying a cacheable area main memory
• turning the MMU on or off
• changing the virtual-to-physical mappings in the MMU page tables
• turning the ICache or DCache on, if its contents are no longer coherent.
The DCache should be cleaned, and both caches invalidated, before the cache and write buffer configuration of an
area of memory is changed by modifying Ctt or Btt in the MMU translation table descriptor. This is not necessary if it
is known that the caches cannot contain any entries from the area of memory whose translation table descriptor is
being modified.
Changing the process ID in CP15 register 13 does not change the contents of the cache or memory, and does not
affect the mapping between cache entries and physical memory locations. It only changes the mapping between
ARM9TDMI addresses and cache entries. This means that changing the process ID does not lead to any coherency
issues. No cache cleaning or cache invalidation is required when the process ID is changed.
At reset the DCache and ICache entries are all invalidated and the DCache and ICache are disabled.
The software design also needs to consider that the pipelined design of the ARM9TDMI core means that it fetches
three instructions ahead of the current execution point. So, for example, the three instructions following an MCR
which invalidates the ICache, will have been read from the ICache before it is invalidated.