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MMU ARM920T PROCESSOR
3-10
TRANSLATING SECTION REFERENCES
Figure 3-5 illustrates the complete section translation sequence. Note that access permissions contained in the level
one descriptor must be checked before the physical address is generated.
31 0
Table index
1920
Section index
0
31 0
Translation base
Translation table base
1314
31 0
Translation base
1314 12
0Table index
18
12
Section level one descriptor
0
31 0
Section base address
12
1Domain
3
B
4
C
5
1
12 11 10 9 8
AP
1920
31 0
Section base address
Physical address
12
20
1920
Section index
Figure 3-5. Section Translation