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S3C2410A PWM TIMER
10-3
PWM TIMER OPERATION
PRESCALER & DIVIDER
An 8-bit prescaler and a 4-bit divider make the following output frequencies:
4-bit divider settings Minimum resolution
(prescaler = 0)
Maximum resolution
(prescaler = 255)
Maximum interval
(TCNTBn = 65535)
1/2 (PCLK = 66.5 MHz) 0.0300 us (33.2500 MHz) 7.6992 us (129.8828 KHz) 0.5045 sec
1/4 (PCLK = 66.5 MHz) 0.0601 us (16.6250 MHz) 15.3984 us (64.9414 KHz) 1.0091 sec
1/8 (PCLK = 66.5 MHz) 0.1203 us ( 8.3125 MHz) 30.7968 us (32.4707 KHz) 2.0182 sec
1/16 (PCLK = 66.5 MHz) 0.2406 us ( 4.1562 MHz) 61.5936 us (16.2353 KHz) 4.0365 sec
BASIC TIMER OPERATION
TCMPn
1 0
TCNTn 3 3 2 1 0 2 1 0 0
Start bit=1 Timer is started TCNTn=TCMPn Auto-reload TCNTn=TCMPn Timer is stopped
TOUTn
Command
Status
TCNTBn=3
TCNTBn=1
Manual update=1
Auto-reload=1
TCNTBn=2
TCNTBn=0
Manual update=0
Auto-reload=1
Interrupt request
Auto-reload
Interrupt request
Figure 10-2. Timer Operations
A timer (except the timer ch-5) has TCNTBn, TCNTn, TCMPBn and TCMPn. (TCNTn and TCMPn are the names of
the internal registers. The TCNTn register can be read from the TCNTOn register) The TCNTBn and the TCMPBn are
loaded into the TCNTn and the TCMPn when the timer reaches 0. When the TCNTn reaches 0, an interrupt request
will occur if the interrupt is enabled.