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PROGRAMMER'S MODEL ARM920T PROCESSOR
2-4
CP15 REGISTER MAP SUMMARY
CP15 defines 16 registers. The register map for CP15 is shown in Table 2-2
Table 2-2. CP15 Register Map
Register Read Write
0 ID code (1) Unpredictable
0 Cache type (1) Unpredictable
1 Control Control
2 Translation table base Translation table base
3 Domain access control Domain access control
4 Unpredictable Unpredictable
5 Fault status (2) Fault status (2)
6 Fault address Fault address
7 Unpredictable Cache operations
8 Unpredictable TLB operations
9 Cache lockdown (2) Cache lockdown (2)
10 TLB lock down (2) TLB lock down (2)
11 Unpredictable Unpredictable
12 Unpredictable Unpredictable
13 Process ID Process ID
14 Unpredictable Unpredictable
15 Test configuration Test configuration
NOTES:
1. Register location 0 provides access to more than one register. The register accessed depends upon the value of the
opcode_2 field. See the register description for details.
2. Separate registers for instruction and data. See the register description for details.