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ARM920T PROCESSOR PROGRAMMER'S MODEL
2-19
REGISTER 9: CACHE LOCK DOWN REGISTER
Register 9 is the cache lock down register. The cache lock down register is 0x0 on reset. The cache lock down
register allows software to control which cache line in the ICache or DCache respectively is loaded for a linefill and to
prevent lines in the ICache or DCache from being evicted during a linefill, locking them into the cache.
There is a register for each of the ICache and DCache, the value of opcode_2 determines which cache register to
access:
opcode_2 = 0x0 causes the DCache register to be accessed
opcode_2 = 0x1 causes the ICache register to be accessed.
The Opcode_1 and CRm fields should be zero.
Reading CP15 register 9 returns the value of the cache lock down register, which is the base pointer for all cache
segments.
NOTE
Only bits [31:26] are returned. Bits [25:0] are unpredictable.
Writing CP15 register 9 updates the cache lock down register, both the base and the current victim pointer for all
cache segments. Bits [25:0] should be zero.
The victim counter specifies the cache line to be used as the victim for the next linefill. This is incremented using
either a random or round-robin replacement policy, determined by the state of the RR-bit in register 1. The victim
counter generates values in the range (base to 63). This locks lines with index values in the range (0 to base-1). If
base = 0, there are no locked lines.
Writing to CP15 register 9 updates the base pointer and the current victim pointer. The next linefill will use and then
increment the victim pointer. The victim pointer will continue incrementing on linefills and will wrap around to the base
pointer. For example, setting the base pointer to 0x3 prevents the victim pointer from selecting entries 0x0 to 0x2,
locking them into the cache.
Load a cache line into ICache line 0 and lock it down:
MCR to CP15 register 9, opcode_2 = 0x1, Victim = Base = 0x0
MCR I prefetch. Assuming the ICache misses, a linefill will occur to line 0.
MCR to CP15 register 9, opcode_2 = 0x1, Victim = Base = 0x1
Further ICache linefills will now occur into lines 1 - 63.
Load a cache line into DCache line 0 and lock it down:
MCR to CP15 register 9, opcode_2 = 0x0, Victim = Base = 0x0
Data load (LDR/LDM). Assuming the DCache misses, a linefill will occur to line 0.
MCR to CP15 register 9, opcode_2 = 0x0, Victim = Base = 0x1
Further DCache linefills will now occur into lines 1 - 63.
NOTE
Writing CP15 register 9, with the CRm field set to 0b0001, updates the current victim pointer only for the
specified segment only. Bits [31:26] specify the victim; bits [7:5] specify the segment (for a 16KB cache)
and all other bits should be zero. This encoding is intended for debug use. It is not necessary and not
advised, to use this encoding.