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PROGRAMMER'S MODEL ARM920T PROCESSOR
2-20
Figure 2-5 shows the format of bits in register 9
31 19 1516 111221 20
0 0
8 7 4 3 0
0 0 0 00Index 0
26 25 24 23 10 9 5
0 0 0 0
2 1
00000000
13141718
0 0 0
22
UNP/SBZ
6
0 0 0
Figure 2-5. Register 9
Table 2-18 shows the instructions needed to access the cache lock down register:
Table 2-18. Accessing the Cache Lock Down Register 9
Function Data Instruction
Read DCache lock down base Base MRC p15,0,Rd,c9,c0,0
Write DCache victim and lockdown base Victim=Base MCR p15,0,Rd,c9,c0,0
Read ICache lock down base Base MRC p15,0,Rd,c9,c0,1
Write ICache victim and lockdown base Victim = Base MCR p15,0,Rd,c9,c0,1