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PROGRAMMER'S MODEL ARM920T PROCESSOR
2-18
REGISTER 8: TLB OPERATIONS
Register 8 is a write-only register used to manage the translation lookaside buffers (TLBs), the instruction TLB and
the data TLB.
Five TLB operations are defined and the function to be performed is selected by the opcode_2 and CRm fields in the
MCR instruction used to write CP15 register 8. Writing other opcode_2 or CRm values is unpredictable. Reading from
CP15 register 8 is unpredictable.
Table 2-17 on page 2-18 shows instructions that can be used to perform TLB operations using register 8.
Table 2-17. TLB Operations Register 8
Function Data Instruction
Invalidate TLB(s) SBZ MCR p15,0,Rd,c8,c7,0
Invalidate I TLB SBZ MCR p15,0,Rd,c8,c5,0
Invalidate I TLB single entry (using MVA) MVA format MCR p15,0,Rd,c8,c5,1
Invalidate D TLB SBZ MCR p15,0,Rd,c8,c6,0
Invalidate D TLB single entry (using MVA) MVA format MCR p15,0,Rd,c8,c6,1
NOTE: These functions invalidate all the un-preserved entries in the TLB.
Invalidate TLB single entry functions invalidate any TLB entry corresponding to the modified virtual address given in
Rd, regardless of its preserved state. See Register 10: TLB lock down register on page 2-21
Figure 2-4 shows the modified virtual address format used for operations on single entry TLB lines using register 8.
31
0
4 3 0
Modified virtual address
5
0000
2 1
0
8 79
000
6
0
10
SBZ
Figure 2-4. Register 8 MVA Format