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CLOCK MODES ARM920T PROCESSOR
5-2
FASTBUS MODE
In this mode of operation the BCLK input is the source for GCLK. The FCLK input is ignored. This mode is typically
used in systems with high speed memory.
SYNCHRONOUS MODE
This mode is typically used in systems with low speed memory. In this mode GCLK can be sourced from BCLK and
FCLK. BCLK is used to control the AMBA memory interface. FCLK is used to control the internal ARM9TDMI
processor core and any cache operations. FCLK must have a higher frequency and must also be an integer multiple
of BCLK, with a BCLK transition only when FCLK is HIGH. An example is shown in Figure 5-2.
FCLK
BCLK
Figure 5-2. Synchronous Clocking Mode
If the ARM920T performs an external access, for example, a cache linefill, the ARM920T will switch to BCLK to
perform the access. The delay when switching from FCLK to BCLK is a minimum of one FCLK phase and a
maximum of one BCLK cycle. An example of the clock switching is shown in Figure 5-3 . The delay when switching
from BCLK to FCLK is a maximum of one FCLK phase.
FCLK
BCLK
ECLK
Figure 5-3. Switching from FCLK to BCLK in Synchronous Mode
Care must be taken if BCLK is stopped by the system so that when BCLK is restarted it does not violate any of the
above restrictions.