NAND FLASH CONTROLLER S3C2410A
6-2
BLOCK DIAGRAM
Buffer
Control
System Bus
CLE
Internal
Buffer
(4KB)
Register
Bank
Control
State
Machine
ECC
Encoder/
Decoder
NAND Flash
Interface
nCE
nRE
nWE
R/nB
I/O0~I/O7
ALE
Figure 6-1. NAND Flash Controller Block Diagram
OPERATION SCHEME
Steppingstone
(4 KB Buffer)
NAND Flash
Controller
NAND
Flash
Memory
Special Function
Registers
Auto Boot Mode
NAND Flash Mode
CPU Access
(Boot Code)
User Access
Figure 6-2. NAND Flash Operation Scheme