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MMU ARM920T PROCESSOR
3-6
HARDWARE TRANSLATION PROCESS
TRANSLATION TABLE BASE
The hardware translation process is initiated when the TLB does not contain a translation for the requested modified
virtual address. The translation table base (TTB) register points to the base address of a table in physical memory
which contains section and/or Page descriptors. The 14 low-order bits of the TTB register are set to zero on a read
and the table must reside on a 16KB boundary.
31 0
Translation table base
1314
Figure 3-2. Translation Table Base Register
The translation table has up to 4096 x 32-bit entries, each describing 1MB of virtual memory. This allows up to 4GB
of virtual memory to be addressed. Figure 3-1 on page 3-5 illustrates the table walk process.