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ARM920T PROCESSOR MMU
3-7
LEVEL ONE FETCH
Bits 31:14 of the translation table base register are concatenated with bits 31:20 of the modified virtual address to
produce a 30-bit address as illustrated in Figure 3-3 on page 3-7.
This address selects a 4-byte translation table entry which is a level one descriptor for either a section or a page
table.
31 0
Table index
1920
Section index
Modified virtual address
0
31 0
Translation base
Translation table base
1314
31 0
Translation base
1314 12
0Table index
18
12
31 0
Level one descriptor
Figure 3-3. Accessing the Translation Table Level One Descriptors