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S3C2410A DMA
8-11
DMA STATUS (DSTAT) REGISTER
Register Address R/W Description Reset Value
DSTAT0 0x4B000014 R DMA 0 count register 000000h
DSTAT1 0x4B000054 R DMA 1 count register 000000h
DSTAT2 0x4B000094 R DMA 2 count register 000000h
DSTAT3 0x4B0000D4 R DMA 3 count register 000000h
DSTATn Bit Description Initial State
STAT [21:20] Status of this DMA controller.
00: Indicates that DMA controller is ready for another DMA request.
01: Indicates that DMA controller is busy for transfers.
00b
CURR_TC [19:0] Current value of transfer count.
Note that transfer count is initially set to the value of DCONn[19:0]
register and decreased by one at the end of every atomic transfer.
00000h
DMA CURRENT SOURCE (DCSRC) REGISTER
Register Address R/W Description Reset Value
DCSRC0 0x4B000018 R DMA 0 current Source Register 0x00000000
DCSRC1 0x4B000058 R DMA 1 current Source Register 0x00000000
DCSRC2 0x4B000098 R DMA 2 current Source Register 0x00000000
DCSRC3 0x4B0000D8 R DMA 3 current Source Register 0x00000000
DCSRCn Bit Description Initial State
CURR_SRC [30:0] Current source address for DMAn 0x00000000