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S3C2410A IIS-BUS INTERFACE
21-5
Table 21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs)
Serial bit per channel 8-bit 16-bit
Serial clock frequency (IISCLK)
@CODECLK = 256fs 16fs, 32fs 32fs
@CODECLK = 384fs 16fs, 32fs, 48fs 32fs, 48fs
IIS-BUS INTERFACE SPECIAL REGISTERS
IIS CONTROL (IISCON) REGISTER
Register Address R/W Description Reset Value
IISCON 0x55000000 (Li/HW, Li/W, Bi/W)
0x55000002 (Bi/HW)
R/W IIS control register 0x100
IISCON Bit Description Initial State
Left/Right channel index
(Read only)
[8] 0 = Left
1 = Right
1
Transmit FIFO ready flag
(Read only)
[7] 0 = empty
1 = not empty
0
Receive FIFO ready flag
(Read only)
[6] 0 = full
1 = not full
0
Transmit DMA service request [5] 0 = Disable
1 = Enable
0
Receive DMA service request [4] 0 = Disable
1 = Enable
0
Transmit channel idle command [3] In Idle state the IISLRCK is inactive (Pause Tx).
0 = Not idle
1 = Idle
0
Receive channel idle command [2] In Idle state the IISLRCK is inactive (Pause Rx).
0 = Not idle
1 = Idle
0
IIS prescaler [1] 0 = Disable
1 = Enable
0
IIS interface [0] 0 = Disable (stop)
1 = Enable (start)
0
NOTES:
1. The IISCON register is accessible for each byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR
instructions or char/short int/int type pointer in Little/Big endian mode.
2. (Li/HW/W): Little/HalfWord/Word
(Bi/HW/W): Big/HalfWord/Word