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I/O PORTS S3C2410A
9-28
GENERAL STATUS REGISTER (GSTATUSn)
Register Address R/W Description Reset Value
GSTATUS0 0x560000AC R External pin status Undefined
GSTATUS1 0x560000B0 R Chip ID 0x32410000
GSTATUS2 0x560000B4 R/W Reset status 0x1
GSTATUS3 0x560000B8 R/W Infrom register 0x0
GSTATUS4 0x560000BC R/W Infrom register 0x0
GSTATUS0 Bit Description
nWAIT [3] Status of nWAIT pin
NCON [2] Status of NCON pin
RnB [1] Status of R/nB pin
nBATT_FLT [0] Status of nBATT_FLT pin
GSTATUS1 Bit Description
CHIP ID [31:0] ID register = 0x32410002
GSTATUS2 Bit Description
PWRST [0] Power on reset, if this bit is set to "1".
The setting is cleared by writing "1" to this bit.
OFFRST [1] Power_OFF reset. The reset after the wakeup from Power_OFF mode.
The setting is cleared by writing "1" to this bit.
WDTRST [2] Watchdog reset. The reset derived from Watchdog timer.
The setting is cleared by writing "1" to this bit.
GSTATUS3 Bit Description
INFORM [31:0] Inform register. This register is cleared by nRESET or watchdog timer.
Otherwise, preserve data value.
GSTATUS4 Bit Description
INFORM [31:0] Inform register. This register is cleared by nRESET or watchdog timer.
Otherwise, preserve data value.