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ELECTRICAL DATA S3C2410A
24-32
Table 24-7. ROM/SRAM Bus Timing Constants
(V
DDi
=V
DDalive
=V
DDiarm
= 1.8V ± 0.15 / 2.0 V ± 0.1 V, T
A
= -40 to 85 °C, V
DDMOP
= 3.3V ± 0.3V)
Parameter Symbol Min Typ Max Unit
ROM/SRAM Address Delay t
RAD
3 – 11 / 10.5 ns
ROM/SRAM Chip select Delay t
RCD
2 – 9 / 8.5 ns
ROM/SRAM Output enable Delay t
ROD
2 – 8 / 7.5 ns
ROM/SRAM read Data Setup time. t
RDS
4 – – ns
ROM/SRAM read Data Hold time. t
RDH
0 – – ns
ROM/SRAM Byte Enable Delay t
RBED
2 – 8 / 7.5 ns
ROM/SRAM Write Byte Enable Delay t
RWBED
2 – 10 / 9.5 ns
ROM/SRAM output Data Delay t
RDD
3 – 12 / 11.5 ns
ROM/SRAM external Wait Setup time t
WS
5 – – ns
ROM/SRAM external Wait Hold time t
WH
0 – – ns
ROM/SRAM Write enable Delay t
RWD
2 – 9 / 8.5 ns
Table 24-8. Memory Interface Timing Constants (3.3V)
(V
DDi
=V
DDalive
=V
DDiarm
= 1.8V ± 0.15 / 2.0 V ± 0.1 V, T
A
= -40 to 85 °C, V
DDMOP
= 3.3V ± 0.3V)
Parameter Symbol Min Typ Max Unit
SDRAM Address Delay t
SAD
2 – 7 / 6.5 ns
SDRAM Chip Select Delay t
SCSD
2 – 6 / 5.5 ns
SDRAM Row active Delay t
SRD
1 – 5 / 4.5 ns
SDRAM Column active Delay t
SCD
1 – 5 / 4.5 ns
SDRAM Byte Enable Delay t
SBED
2 – 6 / 5.5 ns
SDRAM Write enable Delay t
SWD
2 – 6 / 5.5 ns
SDRAM read Data Setup time t
SDS
4 – – ns
SDRAM read Data Hold time t
SDH
0 – – ns
SDRAM output Data Delay t
SDD
2 – 7 / 6.5 ns
SDRAM Clock Enable Delay t
CKED
2 – 5 / 4.5 ns