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CACHES, WRITE BUFFER ARM920T PROCESSOR
4-2
INSTRUCTION CACHE
The ARM920T includes a 16KB instruction cache. The ICache has 512 lines of 32 bytes (8 words), arranged as a 64-
way set-associative cache and uses modified virtual addresses, translated by CP15 register 13 (see Address
translation on page 3-4), from the ARM9TDMI core.
The ICache implements allocate-on-read-miss. Random or round-robin replacement can be selected under software
control via the RR bit (CP15 register 1, bit 14). Random replacement is selected at reset.
Instructions can also be locked in the ICache such that they cannot be overwritten by a linefill. This operates with a
granularity of 1/64th of the cache, which is 64 words (256 bytes).
All instruction accesses are subject to MMU permission and translation checks. Instruction fetches which are
aborted by the MMU will not cause linefills or instruction fetches to appear on the ASB.
For clarity, the I bit (bit 12 in CP15 register 1) is referred to as the Icr bit throughout the following text. The C bit from
the MMU translation table descriptor corresponding to the address being accessed is referred to as Ctt.