Filter
Top Products
xviii S3C2410A MICROPROCESSOR
Table of Contents (Continued)
Appendix 1- ARM920T Introduction
Abuot the Introduction..........................................................................................................................1-1
Processor Functional Block Diagram.....................................................................................................1-2
Appendix 2- Programmer's Model
About rhe Programmer's Model.............................................................................................................2-1
About rhe ARM9TDMI Programmer's Model ...........................................................................................2-2
Data Abort Model ........................................................................................................................2-2
Instruction Set Extension Spaces .................................................................................................2-3
Cp15 Register Map Summary...............................................................................................................2-4
Accessing Cp15 Registers ...........................................................................................................2-5
Register 0: ID Code Register ........................................................................................................2-7
Register 0: Cache Type Register...................................................................................................2-8
Register 1: Control Register..........................................................................................................2-10
Register 2: Translation Table Base (TTB) Register..........................................................................2-12
Register 3: Domain Access Control Register..................................................................................2-13
Register 4: Reserved....................................................................................................................2-14
Register 5: Fault Status Registers ................................................................................................2-14
Register 6: Fault Address Register................................................................................................2-15
Register 7: Cache Operations.......................................................................................................2-15
Register 8: TLB Operations ..........................................................................................................2-18
Register 9: Cache Lock Down Register..........................................................................................2-19
Register 10: TLB Lock Down Register ...........................................................................................2-21
Registers 11-12 & 14: Reserved....................................................................................................2-22
Register 13: Process ID...............................................................................................................2-22
Register 15: Test Configuration Register........................................................................................2-24
Appendix 3- MMU
About the MMU...................................................................................................................................3-1
Access Permissions And Domains ...............................................................................................3-1
Translated Entries .......................................................................................................................3-2
Mmu Program Accessible Registers .....................................................................................................3-3
Address Translation.............................................................................................................................3-4
Hardware Translation Process ..............................................................................................................3-6
Translation Table Base.................................................................................................................3-6
Level One Fetch..........................................................................................................................3-7
Level One Descriptor............................................................................................................................3-8
Section Descriptor...............................................................................................................................3-9
Coarse Page Table Descriptor ..............................................................................................................3-9
Fine Page Table Descriptor ..................................................................................................................3-9
Translating Section References.............................................................................................................3-10