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S3C2410A UART
11-1
11 UART
OVERVIEW
The S3C2410A UART (Universal Asynchronous Receiver and Transmitter) provides three independent asynchronous
serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other words, the UART
can generate an interrupt or a DMA request to transfer data between CPU and the UART. The UART can support bit
rates of up to 230.4K bps using system clock. If an external device provides the UART with UEXTCLK, then the
UART can operate at higher speed. Each UART channel contains two 16-byte FIFOs for receive and transmit.
The S3C2410A UART includes programmable baud rates, infra-red (IR) transmit/receive, one or two stop bit insertion,
5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, a transmitter, a receiver and a control unit, as shown in Figure11-1. The
baud-rate generator can be clocked by PCLK or UEXTCLK. The transmitter and the receiver contain 16-byte FIFOs
and data shifters. Data is written to FIFO and then copied to the transmit shifter before being transmitted. The data
is then shifted out by the transmit data pin (TxDn). Meanwhile, received data is shifted from the receive data pin
(RxDn), and then copied to FIFO from the shifter.
FEATURES
— RxD0, TxD0, RxD1, TxD1, RxD2, and TxD2 with DMA-based or interrupt-based operation
— UART Ch 0, 1, and 2 with IrDA 1.0 & 16-byte FIFO
— UART Ch 0 and 1 with nRTS0, nCTS0, nRTS1, and nCTS1
— Supports handshake transmit/receive