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S3C2410A ARM INSTRUCTION SET
3-33
EXAMPLES
STR R1,[R2,R4]! ; Store R1 at R2+R4 (both of which are registers)
; and write back address to R2.
STR R1,[R2],R4 ; Store R1 at R2 and write back R2+R4 to R2.
LDR R1,[R2,#16] ; Load R1 from contents of R2+16, but don't write back.
LDR R1,[R2,R3,LSL#2] ; Load R1 from contents of R2+R3*4.
LDREQB R1,[R6,#5] ; Conditionally load byte at R6+5 into
; R1 bits 0 to 7, filling bits 8 to 31 with zeros.
STR R1,PLACE ; Generate PC relative offset to address PLACE.
PLACE