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ARM920T PROCESSOR MMU
3-11
LEVEL TWO DESCRIPTOR
If the level one fetch returns either a coarse page table descriptor or a fine page table descriptor, this provides the
base address of the page table to be used. The page table is then accessed and a level two descriptor is returned.
This defines either a tiny, a small or a large page descriptor:
• a tiny page descriptor provides the base address of a 1KB block of memory
• a small page descriptor provides to the base address of a 4KB block of memory
• a large page descriptor provides the base address of a 64KB block of memory
Coarse page tables have 256 entries, each entry describing 4KB. These entries can provide base addresses for
either small or large pages. Large page descriptors must be repeated in 16 consecutive entries.
Fine page tables have 1024 entries, each entry describing 1KB. These entries can provide base addresses for either
tiny, small or large pages. Small page descriptors must be repeated in 4 consecutive entries and large page
descriptors must be repeated in 64 consecutive entries.
The figure below shows the format of level one descriptors.
31 1112 8 4 3 010 9 5
0
Large page base address
Small page base address
0
12
10
01
11
C B
Tiny page base address
Fault
Large page
Small page
Tiny page
ap0
C B
C B
ap0
ap
ap1
ap1
ap2
ap2
ap3
ap3
1516 67
Figure 3-6. Page Table Entry (Level One Descriptor)
Bits[1:0] indicate the page size and validity and are interpreted as follows.
Table 3-3. Interpreting Page Table Entry Bits 1:0
Value Meaning Notes
00 Invalid Generates a page translation fault.
01 Large page Indicates that this is a 64KB page.
10 Small page Indicates that this is a 4KB page.
11 Tiny page Indicates that this is a 1KB page.