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S3C2410A CLOCK & POWER MANAGEMENT
7-7
Change PLL Settings In Normal Operation Mode
During the operation of the S3C2410A in NORMAL mode, the user can change the frequency by writing the PMS
value and the PLL lock time will be automatically inserted. During the lock time, the clock is not supplied to the
internal blocks in the S3C2410A. Figure 7-5 shows the timing diagram.
Mpll
PMS setting
PLL Lock-time
FCLK
It changes to new PLL clock
after automatic lock time.
Figure 7-5. Changing Slow Clock by Setting PMS Value
USB Clock Control
USB host interface and USB device interface needs 48Mhz clock. In the S3C2410A, the USB dedicated PLL (UPLL)
generates 48MHz for USB. UCLK does not fed until the PLL (UPLL) is configured.
Condition UCLK State UPLL State
After reset XTlpll or EXTCLK On
After configuring UPLL L : during PLL lock time
48MHz: after PLL lock time
On
UPLL is turned off by CLKSLOW register XTlpll or EXTCLK Off
UPLL is turned on by CLKSLOW register 48MHz On