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MMU ARM920T PROCESSOR
3-12
Bit 3:2 (C & B) indicate whether the area of memory mapped by this page is treated as write-back cacheable, write-
through cacheable, non cached buffered or non-cached non-buffered.
Domain access control on page 3-19 and Fault checking sequence on page 3-21 show how to interpret the access
permission (ap) bits.
NOTE
Tiny pages do not support sub page permissions and therefore only have one set of access permission bits.
Bits 31:10 (tiny pages), 31:12 (small pages) or bits 31:16 (large pages) are used to form the corresponding bits of the
physical address.
TRANSLATING LARGE PAGE REFERENCES
Figure 3-7 on page 3-13 illustrates the complete translation sequence for a 64KB large page.
As the upper four bits of the page index and low-order four bits of the coarse page table index overlap, each coarse
page table entry for a large page must be duplicated 16 times (in consecutive memory locations) in the coarse page
table.
If a large page descriptor is included in a fine page table the upper six bits of the page index and low-order six bits of
the fine page table index overlap, each fine page table entry for a large page must therefore be duplicated 64 times.