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NAND FLASH CONTROLLER S3C2410A
6-4
PIN CONFIGURATION
D[7:0] : Data/Command/Address In/Out Port (shared with the data bus)
CLE : Command Latch Enable (Output)
ALE : Address Latch Enable (Output)
nFCE : NAND Flash Chip Enable (Output)
nFRE : NAND Flash Read Enable (Output)
nFWE : NAND Flash Write Enable (Output)
R/nB : NAND Flash Ready/nBusy (Input)
BOOT AND NAND FLASH CONFIGURATIONS
1. OM[1:0] = 00b : Enable NAND flash controller auto boot mode
2. NAND flash memory page size should be 512Bytes.
3. NCON : NAND flash memory address step selection
0 : 3 Step addressing
1 : 4 Step addressing
512-BYTE ECC PARITY CODE ASSIGNMENT TABLE
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ECC0 P64 P64’ P32 P32’ P16 P16’ P8 P8’
ECC1 P1024 P1024’ P512 P512’ P256 P256’ P128 P128’
ECC2 P4 P4’ P2 P2’ P1 P1’ P2048 P2048’
S3C2410A generates 512-Byte ECC Parity Code during Write/Read operation. ECC Parity Code consists of 3 Bytes
per 512-Byte data.
24-bit ECC Parity Code = 18-bit Line parity + 6-bit Column Parity
ECC generator block executes the followings:
1. When MCU writes data to NAND, the ECC generator block generates ECC code.
2. When MCU reads data from NAND, the ECC generator block generates ECC code and users compare it with
pre-written ECC code.