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S3C2410A PRODUCT OVERVIEW
1-21
Table 1-3. S3C2410A Signal Descriptions (Continued)
Signal I/O Descriptions
NAND Flash
CLE O Command Latch Enable
ALE O Address Latch Enable
nFCE O NAND Flash Chip Enable
nFRE O NAND Flash Read Enable
nFWE O NAND Flash Write Enable
NCON I NAND Flash Configuration.
If NAND Flash Controller isn't used, it has to be tied on pull-up resistor.
R/nB I NAND Flash Ready/Busy.
If NAND Flash Controller isn't used, it has to be tied on pull-up resistor.
LCD Control Unit
VD [23:0] O STN/TFT/SEC TFT: LCD Data Bus
LCD_PWREN O STN/TFT/SEC TFT: LCD panel power enable control signal
VCLK O STN/TFT: LCD clock signal
VFRAME O STN: LCD Frame signal
VLINE O STN: LCD line signal
VM O STN: VM alternates the polarity of the row and column voltage
VSYNC O TFT: Vertical synchronous signal
HSYNC O TFT: Horizontal synchronous signal
VDEN O TFT: Data enable signal
LEND O TFT: Line End signal
STV O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
CPV O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
LCD_HCLK O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
TP O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
STH O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
LCDVF [2:0] O SEC TFT: Timing control signal for specific TFT LCD (OE/REV/REVB)
Interrupt Control Unit
EINT [23:0] I External Interrupt request
DMA
nXDREQ [1:0] I External DMA request
nXDACK [1:0] O External DMA acknowledge