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S3C2410A LCD CONTROLLER
15-15
TFT LCD CONTROLLER OPERATION
The TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND
signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the
REGBANK. Base on these programmable configurations on the LCD control registers in the REGBANK, the
TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD
drivers.
The VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display.
The VSYNC and HSYNC pulse generation depends on the configurations of both the HOZVAL field and the LINEVAL
field in the LCDCON2/3 registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel
according to the following equations:
HOZVAL = (Horizontal display size) -1
LINEVAL = (Vertical display size) -1
The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register. Table 15-3 defines the relationship
of VCLK and CLKVAL. The minimum value of CLKVAL is 0.
VCLK(Hz)=HCLK/[(CLKVAL+1)x2]
The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD,
LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL in LCDCON1 and LCDCON2/3/4 registers. Most LCD
drivers need their own adequate frame rate. The frame rate is calculated as follows:
Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } × {(HSPW+1) + (HBPD +1)
+ (HFPD+1) + (HOZVAL + 1) } × { 2 × ( CLKVAL+1 ) / ( HCLK ) } ]
Table 15-3. Relation Between VCLK and CLKVAL (TFT, HCLK = 60 MHz)
CLKVAL 60 MHz/X VCLK
1 60 MHz/4 15.0 MHz
2 60 MHz/6 10.0 MHz
: : :
1023 60 MHz/2048 30.0 kHz
VIDEO OPERATION
The TFT LCD controller within the S3C2410A supports 1, 2, 4 or 8 bpp (bit per pixel) palettized color displays and 16
or 24 bpp non-palettized true-color displays.
256 Color Palette
The S3C2410A can support the 256 color palette for various selection of color mapping, providing flexible operation
for users.