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ARM920T PROCESSOR INTRODUCTION
1-1
Appendix 1
ARM920T INTRODUCTION
ABUOT THE INTRODUCTION
The ARM920T is a member of the ARM9TDMI family of general-purpose microprocessors, which includes:
— ARM9TDMI (ARM9TDMI core)
— ARM940T (ARM9TDMI core plus cache and protection unit)
— ARM920T (ARM9TDMI core plus cache and MMU).
The ARM9TDMI processor core is a Harvard architecture device implemented using a five-stage pipeline consisting of
fetch, decode, execute, memory and write stages, and can be provided as a stand-alone core which can be
embedded into more complex devices. The stand-alone core has a simple bus interface that allows users to design
their own caches/memory systems around it.
The ARM9TDMI family of microprocessors supports both the 32-bit ARM and 16-bit Thumb instruction sets, allowing
the user to trade off between high performance and high code density.
The ARM920T is a Harvard cache architecture processor which is targeted at multiprogrammer applications where
full memory management, high performance, and low power are all-important. The separate instruction and data
caches in this design are 16KB each in size, with an 8-word line length. The ARM920T implements an enhanced
ARM Architecture V4 MMU to provide translation and access permission checks for instruction and data addresses.
The ARM920T supports the ARM debug architecture and includes logic to assist in both hardware and software
debug. The ARM920T also includes support for coprocessors, exporting the instruction and data buses along with
simple handshaking signals.
The ARM920T interface to the rest of the system is via unified address and data buses. This interface is compatible
with the Advanced Microcontroller Bus Architecture (AMBA) bus scheme, either as a fully compliant AMBA bus
master, or as a slave for production test. The ARM920T also has a TrackingICE mode which allows an approach
similar to a conventional ICE mode of operation.