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ARM920T PROCESSOR MMU
3-21
FAULT CHECKING SEQUENCE
The sequence by which the MMU checks for access faults is different for sections and pages. The sequence for both
types of access is shown below. The conditions that generate each of the faults are described on the following
pages.
Modified virtual address
Check address alignment
Get level one descriptor
Section Page
Get page
table entry
Check domain status
Section Page
Client(01)Client(01)
Manager(11)
Check access
permissions
Check access
permissions
Physical address
Alignment
fault
Page
translation
fault
Page
domain
fault
Misaligned
Invalid
No access(00)
Reserved(10)
Page
permission
fault
Violation
Section
domain
fault
No access(00)
Reserved(10)
Section
permission
fault
Violation
Section
translation
fault
Invalid
Figure 3-11. Sequence for Checking Faults