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S3C2410A CLOCK & POWER MANAGEMENT
7-9
POWER MANAGEMENT
The power management block controls the system clocks by software for the reduction of power consumption in the
S3C2410A. These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals.
Figure 7-7 shows the clock distribution of the S3C2410A.
The S3C2410A has four power modes. The following section describes each power management mode. The
transition between the modes is not allowed freely. For available transitions among the modes, see Figure 7-8.
INTCNTL
Power
Management
FCLK
Input Clock
FCLK defination
If SLOW mode
FCLK = input clock/divider ratio
If Normal mode (P, M & S value)
FCLK = MPLL clock (Mpll)
ARM920T
HCLK
PCLK
UCLK (48 MHz)
BUSCNTL
MEMCNTL
ARB/DMA
ExtMaster
LCDCNTL
Nand Flash
Controller
USB
Host I/F
WDT
SPI
PWM
I2C
SDI
ADC
UART
I2S
GPIO
RTC
USB
Device
Clock Control
Register
Figure 7-7. The Clock Distribution Block Diagram