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S3C2410A USB DEVICE
13-13
END POINT0 CONTROL STATUS REGISTER (EP0_CSR) (Continued)
EP0_CSR Bit MCU USB Description Initial State
IN_PKT_RDY [1] SET CLEAR Set by the MCU after writing a packet of data
into EP0 FIFO. The USB clears this bit once
the packet has been successfully sent to the
host. An interrupt is generated when the USB
clears this bit, so as the MCU to load the next
packet. For a zero length data phase, the
MCU sets DATA_END at the same time.
0
OUT_PKT_RDY [0] R SET Set by the USB once a valid token is written
to the FIFO. An interrupt is generated when
the USB sets this bit. The MCU clears this bit
by writing a "1" to the
SERVICED_OUT_PKT_RDY bit.
0