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S3C2410A BUS PRIORITIES
23-1
23 BUS PRIORITIES
OVERVIEW
The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode
and fixed priority mode.
BUS PRIORITY MAP
The S3C2410A holds eleven bus masters including SDRAM refresh controller, LCD_DMA, DMA0, DMA1, DMA2,
DMA3, USB_HOST_DMA, EXT_BUS_MASTER, Test interface controller (TIC), and ARM920T. The following list
shows the priorities among these bus masters after a reset:
1. SDRAM refresh controller
2. LCD_DMA
3. DMA0
4. DMA1
5. DMA2
6. DMA3
7. USB host DMA
8. External bus master
9. TIC
10. ARM920T
11. Reserved
Among those bus masters, four DMAs operate under the rotation priority, while others run under the fixed priority.