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SPI INTERFACE S3C2410A
22-8
SPI STATUS REGISTER
Register Address R/W Description Reset Value
SPSTA0 0x59000004 R SPI channel 0 status register 0x01
SPSTA1 0x59000024 R SPI channel 1 status register 0x01
SPSTAn Bit Description Initial State
Reserved [7:3]
Data Collision Error Flag
(DCOL)
[2] This flag is set if the SPTDATn is written or the SPRDATn is
read while a transfer is in progress and cleared by reading
the SPSTAn.
0 = not detect, 1 = collision error detect
0
Multi Master Error Flag
(MULF)
[1] This flag is set if the nSS signal goes to active low while the
SPI is configured as a master, and SPPINn's ENMUL bit is
multi master errors detect mode. MULF is cleared by
reading SPSTAn.
0 = not detect, 1 = multi master error detect
0
Transfer Ready Flag
(REDY)
[0] This bit indicates that SPTDATn or SPRDATn is ready to
transmit or receive. This flag is automatically cleared by
writing data to SPTDATn.
0 = not ready, 1 = data Tx/Rx ready
1