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CACHES, WRITE BUFFER ARM920T PROCESSOR
4-12
CACHE CLEANING WHEN LOCKDOWN IS IN USE
The clean D single entry (using index) and clean and invalidate D entry (using index) operations can leave the victim
pointer set to the index value used by the operation. In some circumstances, if DCache locking is in use, this could
leave the victim pointer in the locked region, leading to locked data being evicted from the cache. The victim pointer
can be moved outside the locked region by implementing the cache loop enclosed by the reading and writing of the
Base and Victim pointer:
MRC p15, 0, Rd, c9, c0, 0 ; Read D Cache Base into Rd
Index Clean or Index Clean and Invalidate loops
MCR p15, 0, Rd, c9, c0, 0 ; Write D Cache Base and Victim from Rd
Clean D single entry (using VA) and clean and invalidate D entry (using VA) operations do not move the victim
pointer, so there is no need to reposition the victim pointer after using these operations.
IMPLEMENTATION NOTES
This section describes the behavior of the ARM920T implementation in areas which are architecturally unpredictable.
For portability to other ARM implementations, software should not depend on this behavior.
A read from a non-cacheable (NCB or NCNB) region which unexpectedly hits in the cache will still read the required
data from the ASB. The contents of the cache will be ignored, and the cache contents will not be modified. This
includes the read portion of a swap (SWP or SWPB) instruction.
A write to a non-cacheable (NCB or NCNB) region which unexpectedly hits in the cache will update the cache and
will still cause an access on the ASB.
PHYSICAL ADDRESS TAG RAM
The ARM920T implements a PA TAG RAM in order to perform write backs from the data cache.
A write back occurs when dirty data that is about to be overwritten by linefill data comes from a memory region that
is marked as a write back region. This data is written back to main memory to maintain memory coherency.
Dirty data is data that has been modified in the cache, but not updated in main memory.
When a line is written into the data cache, the physical address TAG (DPA[31:5]) is written into the PA TAG RAM. If
this line comes to be written back to main memory, the PA TAG RAM is indexed into by the data cache and the
physical address (WBPA[31:0]) is returned to the AMBA Bus interface so that it can perform the write back.
The PA TAG RAM Array for a 16k data cache comprises 8 segments x 64 rows/segment x 26 bits/row. There are
two test interfaces to the PA TAG RAM:
Debug interface, see Scan chain 4 - debug access to the PA TAG RAM
AMBA test interface, see PA TAG RAM test