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MEMORY CONTROLLER S3C2410A
5-6
nXBREQ/nXBACK Pin Operation
If nXBREQ is asserted, the S3C2410A will respond by lowering nXBACK. If nXBACK = L, the address/data bus and
memory control signals are in Hi-z state as shown in Table 1-1. When nXBREQ is de-asserted, the nXBACK will also
be de-asserted.
HCLK
SCKE, A[24:0]
D[31:0],nGCS
nOE,nWE
nWBE
nXBREQ
~
~
~
~
nXBACK
~
~
~
~
1CLK
SCLK
Figure 5-3. S3C2410A nXBREQ/nXBACK Timing Diagram