Samsung S3C2410A Microphone User Manual


 
S3C2410A PRODUCT OVERVIEW
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Table 1-3. S3C2410A Signal Descriptions (Continued)
Signal I/O Description
SD
SDDAT [3:0] IO SD receive/transmit data
SDCMD IO SD receive response/ transmit command
SDCLK O SD clock
General Port
GPn [116:0] IO General input/output ports (some ports are output only)
TIMMER/PWM
TOUT [3:0] O Timer Output [3:0]
TCLK [1:0] I External timer clock input
JTAG TEST LOGIC
nTRST I nTRST (TAP Controller Reset) resets the TAP controller at start.
If debugger is used, A 10K pull-up resistor has to be connected.
If debugger (black ICE) is not used, nTRST pin must be issued by a low active pulse
(Typically connected to nRESET).
TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's
states. A 10K pull-up resistor has to be connected to TMS pin.
TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.
A 10K pull-up resistor must be connected to TCK pin.
TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data.
A 10K pull-up resistor must be connected to TDI pin.
TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and data.
Reset, Clock & Power
nRESET ST nRESET suspends any operation in progress and places S3C2410A into a known
reset state. For a reset, nRESET must be held to L level for at least 4 FCLK after the
processor power has been stabilized.
nRSTOUT O For external device reset control
(nRSTOUT = nRESET & nWDTRST & SW_RESET)
PWREN O 2.0V core power on-off control signal
nBATT_FLT I Probe for battery state (Does not wake up at power-off mode in case of low battery
state). If it isn't used, it has to be High (3.3V).
OM [3:2] I OM [3:2] determines how the clock is made.
OM [3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source.
OM [3:2] = 01b, Crystal is used for MPLL CLK source
and EXTCLK is used for UPLL CLK source.
OM [3:2] = 10b, EXTCLK is used for MPLL CLK source
and Crystal is used for UPLL CLK source.
OM [3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.