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S3C2410A MICROPROCESSOR xxiii
List of Figures (Continued)
Figure Title Page
Number Number
6-1 NAND Flash Controller Block Diagram...................................................................6-2
6-2 NAND Flash Operation Scheme............................................................................6-2
6-3 TACLS = 0, TWRPH0 = 1, TWRPH1 = 0...............................................................6-3
6-4 NAND Flash Memory Mapping..............................................................................6-5
7-1 Clock Generator Block Diagram............................................................................7-3
7-2 PLL (Phase-Locked Loop) Block Diagram..............................................................7-5
7-3 Main Oscillator Circuit Examples ..........................................................................7-5
7-4 Power-On Reset Sequence (when the external clock source is a crystal oscillator) ...7-6
7-5 Changing Slow Clock by Setting PMS Value..........................................................7-7
7-6 Changing CLKDIVN Register Value.......................................................................7-8
7-7 The Clock Distribution Block Diagram....................................................................7-9
7-8 Power Management State Diagram.......................................................................7-10
7-9 Issuing Exit_from_Slow_mode Command in PLL on State.......................................7-12
7-10 Issuing Exit_from_Slow_mode Command After Lock Time.......................................7-12
7-11 Issuing Exit_from_Slow_mode Command and the Instant PLL_on
Command Simultaneously....................................................................................7-13
7-12 Power_OFF Mode ...............................................................................................7-16
8-1 Basic DMA Timing Diagram..................................................................................8-3
8-2 Demand/Handshake Mode Comparison.................................................................8-4
8-3 Burst 4 Transfer Size...........................................................................................8-5
8-4 Single service in Demand Mode with Unit Transfer Size...........................................8-6
8-5 Single service in Handshake Mode with Unit Transfer Size......................................8-6
8-6 Whole service in Handshake Mode with Unit Transfer Size......................................8-6
10-1 16-bit PWM Timer Block Diagram.........................................................................10-2
10-2 Timer Operations.................................................................................................10-3
10-3 Example of Double Buffering Function ...................................................................10-4
10-4 Example of a Timer Operation...............................................................................10-6
10-5 Example of PWM................................................................................................10-7
10-6 Inverter On/Off.....................................................................................................10-8
10-7 The Wave form when a Dead Zone Feature is Enabled............................................10-9
10-8 Timer4 DMA Mode Operation................................................................................10-10
11-1 UART Block Diagram (with FIFO)..........................................................................11-2
11-2 UART AFC Interface............................................................................................11-4
11-3 UART Receiving 4 Characters with 1 Error .............................................................11-6
11-4 IrDA Function Block Diagram................................................................................11-8
11-5 Serial I/O Frame Timing Diagram (Normal UART)....................................................11-9
11-6 Infra-Red Transmit Mode Frame Timing Diagram.....................................................11-9
11-7 Infra-Red Receive Mode Frame Timing Diagram......................................................11-9
11-8 nCTS and Delta CTS Timing Diagram....................................................................11-18
12-1 USB Host Controller Block Diagram......................................................................12-1
13-1 USB Device Controller Block Diagram ...................................................................13-2