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ARM920T PROCESSOR PROGRAMMER'S MODEL
2-1
Appendix 2
PROGRAMMER'S MODEL
ABOUT THE PROGRAMMER'S MODEL
ARM920T incorporates the ARM9TDMI integer core, which implements the ARMv4T architecture. It executes the
ARM and Thumb instruction sets, and includes Embedded ICE JTAG software debug features.
The programmer's model of the ARM920T consists of the programmer's model of the ARM9TDMI with the following
additions and modifications:
• The ARM920T incorporates two coprocessors:
— CP14, which allows software access to the debug communications channel. The registers defined in
CP14 are accessible with MCR and MRC instructions.
— The system control coprocessor (CP15), which provides additional registers that are used to configure
and control the caches, MMU, protection system, the clocking mode and other system options of the
ARM920T, such as big or little-endian operation. The registers defined in CP15 are accessible with MCR
and MRC instructions. These are described in CP15 register map summary on page 2-4.
• The ARM920T also features an external coprocessor interface which allows the attachment of a closely coupled
coprocessor on the same chip, for example, a floating point unit. Registers and operations provided by any
coprocessors attached to the external coprocessor interface will be accessible with appropriate coprocessor
instructions.
• Memory accesses for instruction fetches and data loads and stores may be cached or buffered. Cache and write
buffer configuration and operation is described in detail in following chapters.
• The MMU page tables which reside in main memory describe the virtual to physical address mapping, access
permissions, and cache and write buffer configuration. These are created by the operating system software and
accessed automatically by the ARM920T MMU hardware whenever an access causes a TLB miss.
• The ARM920T has a Trace Interface Port which allows the use of Trace hardware and tools for real-time tracing
of instructions and data.