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S3C2410A IIS-BUS INTERFACE
21-7
IIS PRESCALER (IISPSR) REGISTER
Register Address R/W Description Reset Value
IISPSR 0x55000008 (Li/HW, Li/W, Bi/W)
0x5500000A (Bi/HW)
R/W IIS prescaler register 0x0
IISPSR Bit Description Initial State
Prescaler control A [9:5] Data value: 0 ~ 31
Note: Prescaler A makes the master clock that is used the
internal block and division factor is N+1.
00000
Prescaler control B [4:0] Data value: 0 ~ 31
Note: Prescaler B makes the master clock that is used the
external block and division factor is N+1.
00000
NOTES:
1. The IISPSR register is accessible for each byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR
instructions or char/short int/int type pointer in Little/Big endian mode.
2. (Li/HW/W) : Little/HalfWord/Word.
(Bi/HW/W) : Big/HalfWord/Word.